1. Technical Field
The present invention relates to an offset voltage correction apparatus and an offset voltage correction method for correcting an input offset voltage in a comparator circuit.
2. Background Art
In an operational amplifier constituting a comparator circuit, an input offset voltage, which should be ideally at 0V, has a certain value due to:
(1) Variations in size of transistors located at the input stage of the operational amplifier; and
(2) Temperature drift and deterioration with time.
An operational amplifier having an input offset voltage would cause the comparator circuit to deliver an unexpected signal even when signals at the same voltage level are applied to the positive phase input terminal and the negative input terminal of the operational amplifier. In particular, in such devices as operated with signals of very small amplitude, a slight variation in voltage level would exert significant effects on the circuit in a subsequent stage, thus requiring some means for correcting the input offset voltage with high accuracy.
Prior art techniques for correcting input offset voltages are disclosed in Japanese Patent Kokai No. 11-88071 (Document 1) and Japanese Patent Kokai No. 2001-44770 (Document 2).
Document 1 describes an offset voltage correction circuit comprising a counter circuit. The voltage level of an input signal at which a change occurs in the output signal from the operational amplifier is associated with a counter value of the counter circuit. The input offset voltage is corrected in accordance with this counter value. An amplifier circuit described in Document 2 comprises a comparator circuit for comparing the output voltage from the operational amplifier with a reference voltage and a level shift circuit for adjusting the input voltage to the operational amplifier in accordance with the output signal from this comparator circuit. This circuit arrangement provides a correction to the input offset voltage in the operational amplifier.
The input offset voltages each measured at a transition from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d and from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d in output signal using a prior art comparator circuit were found to be different from each other. That is, the measurements showed that the input offset voltages were different depending on whether the state is at xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d immediately before the change occurs in the output from the comparator circuit, the phenomenon of which is caused by the comparator circuit having a hysteresis characteristic.
In particular, in a device operated with signals of very small amplitude, it is necessary to correct the input offset voltage in the comparator circuit with higher accuracy, without neglecting the deviation in the input offset voltage as described above.
The present invention was devised in view of the aforementioned problems. It is therefore an object of the invention to provide an improved inventive method and apparatus for correcting an offset voltage, the method and apparatus enabling an input offset voltage in the comparator circuit to be corrected with very high accuracy.
To solve the aforementioned problems, according to a first aspect of the present invention, provided is an offset voltage correction apparatus having a comparator internally or externally. The comparator comprises a first internal node having a potential varied in response to a potential at a first input terminal and a second internal node having a potential varied in response to a potential at a second input terminal. The comparator compares the potential at the first internal node with the potential at the second internal node to output a comparison result as a comparison result signal. Furthermore, the offset voltage correction apparatus comprises an offset voltage detection signal output part, an offset voltage correction signal generator, and an offset voltage adjuster.
The offset voltage detection signal output part functions to sequentially convert a counter value obtained through an up-count operation and a down-count operation on a clock signal to an offset voltage detection signal to provide the offset voltage detection signal to the second input terminal of the comparator circuit having a reference signal directed to the first input terminal.
The offset voltage correction signal generator performs a predetermined arithmetic operation, using a counter value provided when a change has occurred in logic level of the comparison result signal during the up-count operation on the clock signal by the offset voltage detection signal output part and using a counter value provided when a change has occurred in logic level of the comparison result signal during the down-count operation on the clock signal by the offset voltage detection signal output part, to generate an offset voltage correction signal in accordance with an arithmetic operation result counter value obtained by the arithmetic operation.
The offset voltage adjuster adjusts the potential at the first internal node or the potential at the second internal node in accordance with the offset voltage correction signal.
According to the offset voltage correction apparatus configured as described above, during an offset correction operation, both the offset voltages are taken into consideration which appear when the potential at the first input terminal of the comparator circuit has changed from a lower level to a higher level than the potential at the second input terminal and from a higher level to a lower level than the potential at the second input terminal. Therefore, even when the comparator circuit has a hysteresis characteristic in terms of an offset voltage, the offset voltage can be corrected with high accuracy. To provide more improved correction accuracy, defined as an arithmetic operation result counter value is an average value of a counter value provided when a change has occurred in logic level of the comparison result signal during the up-count operation on the clock signal by the offset voltage detection signal output part and a counter value provided when a change has occurred in logic level of the comparison result signal during the down-count operation on the clock signal by the offset voltage detection signal output part.
A transistor can constitute the offset voltage adjuster. A first power supply terminal of the transistor is connected to a power supply node, while a second power supply terminal is connected to the first internal node or the second internal node. The offset voltage correction signal, which is directed to a control terminal, provides an ON/OFF control to the transistor.
The offset voltage adjuster can be contained in a first internal node potential control device for controlling the potential at the first internal node in response to the potential at the first input terminal. On the other hand, the offset voltage adjuster can also be contained in a second internal node potential control device for controlling the potential at the second internal node in response to the potential at the second input terminal.
In this case, the first internal node potential control device (or the second internal node potential control device) is preferably a transistor having two control terminals (e.g., a neuron MOS transistor). The voltage at the first input terminal (the second input terminal) is applied to one of the two control terminals or the first control terminal, while the offset voltage correction signal is directed to the other terminal or the second control terminal. On the other hand, the first power supply terminal of the transistor is connected to the power supply node, while the second power supply terminal is connected to the first internal node (the second internal node). This transistor can be employed to thereby reduce the circuit scale of an offset voltage corrector.
According to a second aspect of the present invention, provided is a method for correcting an offset voltage in a comparator with a first internal node having a potential varied in response to a potential at a first input terminal and with a second internal node having a potential varied in response to a potential at a second input terminal.
The comparator compares the potential at the first internal node with the potential at the second internal node to output a comparison result as a comparison result signal. This correction method comprises the following six steps.
In the first step, an up-count operation is performed on a clock signal, and the resulting count value ({overscore (a)} digital value) is sequentially converted to an offset voltage detection signal (an analog value).
In the second step, the offset voltage detection signal obtained in the first step is continually supplied to the second input terminal of the comparator circuit. At this time, a reference signal is supplied to the first input terminal of the comparator circuit.
The up-count operation on the clock signal is stopped a predetermined period of time (at least one or more cycles of the clock signal) after a change has occurred in logic level of the comparison result signal delivered from the comparator circuit. This is the third step. Furthermore, in this third step, a down-count operation on the clock signal is started with respect to a count value provided when the up-count operation has been stopped to sequentially convert the count value obtained through the down-count operation to an offset voltage detection signal.
In the fourth step, the offset voltage detection signal obtained in the third step is continually supplied to the second input terminal of the comparator circuit having a reference signal directed to the first input terminal.
In the fifth step, performed is a predetermined arithmetic operation, using a count value provided when a change has occurred in logic level of the comparison result signal in the second step and a count value provided when a change has occurred in logic level of the comparison result signal in the fourth step, to generate an offset voltage correction signal in accordance with an arithmetic operation result counter value obtained by the arithmetic operation.
Finally, in the sixth step, the potential at the first internal node or at the second internal node is adjusted in accordance with the offset voltage correction signal.
According to the method described above, both the offset voltages can be grasped which appear when the potential at the first input terminal of the comparator circuit has changed from a lower level to a higher level than the potential at the second input terminal and from a higher level to a lower level than the potential at the second input terminal. Therefore, even when the comparator circuit has a hysteresis property in terms of an offset voltage, the offset voltage can be corrected with high accuracy. To provide more improved correction accuracy, defined as an arithmetic operation result counter value is an average value of a count value provided when a change has occurred in logic level of the comparison result signal in the second step and a count value provided when a change has occurred in logic level of the comparison result signal in the fourth step.
On the other hand, the up-count operation on the clock signal in the first step may be interchanged with the down-count operation on the clock signal in the third step.